FAQ: Plug and Play


Microsoft Windows 95

Q: What is Plug and Play?

A: Plug and Play is both a design philosophy and a set of PC architecture specifications. Its goal is to make the PC, add-in hardware devices, drivers and operating system work together automatically without user intervention. In order to achieve this, all components need to be Plug and Play compatible.

Q: What are the components of Plug and Play?


Q: How are devices configured in a Plug and Play System?

A: In order for the system to boot, the BIOS must configure a display device, an input device and a device for initial program loading. Then, it must pass the information about each of these devices to the operating system for additional system configuration.

When devices are added and removed, the three components of a Plug and Play system coordinate and perform the following tasks.

Q: What are the benefits of Plug and Play?


Q: What is NVRAM?

A: NVRAM refers to Non-Volatile RAM. Plug and Play implementation requires 4K of NVRAM (non-volatile RAM) to store some configuration information or the ESCD (Extended System Configuraiton Data) structure. This is also used by Windows 95 to store the information on resources used by legacy (non-Plug and Play) ISA cards. BIOS has a BIOS function call to update this NVRAM.

So, Flash memory is needed so that the BIOS can write into it. NVRAM cannot be written into EPROM since EPROM is read-only. So, a plug and Play BIOS must be programmed in a Flash memory.

Q: What brands of Flash Memory can support NVRAM?

A: Presently, only Intel, SST and Winbond Flash Memories can support NVRAM. The reason for this is because these Flash Memories support the "block erase function". Block erase means that the Flash Memory can be updated block by block. So, when NVRAM is being updated, only the 4K block is being written to and the whole BIOS is not destroyed. Since Windows 95 requires full Plug and Play support, Intel, SST and Winbond are needed. The BIOS should also have full Plug and Play support.

* 1H'95 -P6-133/150MHz positioned at server, workstation and professional desktop. -P6-166MHz will be launched in Q1'96 and position as the Premium stage.


Pipelined Burst SRAM

Q: What is Pipelined Burst SRAM?

A: Through Pipelined Burst SRAM, it would generate burst address and data in synchronization with the CPU.

Q: What are the advantages of Pipelined Burst SRAM?


The P.B. SRAM vs. Asychronous SRAM.
BURST READ3-1-1-13-2-2-2
BURST WRITE3-1-1-14-3-3-3
P. BACK -TO-3-1-1-1N/A
BACK READ1-1-1-1


Shared Memory Buffer Architecture

Q: What is SMBA?

A: The specification was defined by Intel and industry-leading graphic controller vendors (such as S#, Cirrus . . .) This architecture outlines the protocol for graphic controllers to "share" portions of main memory.

Intel is not alone in providing the supporting chipsets. Other candidates such as SIS, ALI, VIA & UMC are joining in the same playing field. But SIS is the first company to implement the specification.

There are many graphic controller vendors such as Cirrus, S3, ATI, Tseng Lab, Trident, IGS . . . developing their new products in conformity to this specitication. It's expected to see more graphic vendors lining up for this new structure.

Leading BIOS vendors also contribute their efforts to the development.

Q: What is the advantage of SMBA?


All the above benefits are reinforcing a company's competitiveness.

Q: What is the impact over system performance?

A: Because a portion of main memory is shared exclusively for graphics, this first impact will be the available memory on Windows applications. Overall system performance is slacked by 5~10% with L2 cache and by 10~20% without L2 cache.

The Chart below shows various combination of price/performance ratio based on an 8MB system (The source is from Intel)

The 2nd impact is the utilization of memory bus. Due to the fact that graphic controllers do not have a dedicated memory bus, it has to share the same bus in main memory. To maneuver the traffic on memory bus effectively and efficiently requires intelligent use of the memory interface and efficient arbitration protocol.

Below is the comparison chart between "shared" and "non-shared" memory benchmarks based on SiS chipsets systems performance.

WinStone 95WinBench 95
Async. SRAM+SharedNon-SharedRatioShared Non-SharedRatio
CPU 75 MHz117.6 125.50.93710.611.10.955
CPU 90 MHz132.2142.20.93012.413.30.932
CPU 100 MHz140.8150.20.93713.714.20.965

WinStone 95WinBench 95
P.B.SRAM+SharedNon-SharedRatioShared Non-SharedRatio
CPU 75 MHz123.3 132.10.93311.612.10.959
CPU 90 MHz138.7146.40.94713.514.70.918
CPU 100 MHz148.1157.30.94214.715.90.925

Test Configuration:

CPU: Pentium - 100MHzMonitor: Viewsonic 17"
Chipsets: SiS 511/12/13M/B BIOS: Phoenix BIOS V0.9
On Board VGA-SiS 6205/5513VGA Memory Clock: 55 MHz
Non-Shared VGA: SiS 6205VGA Mode: 1024x768x256
HDD: Conner CFA 1275AP.B.SRAM: HM6203232FP8.256K
VGA BIOS: SiS V0.53Async. SRAM: ISSI - 15, 256K
O.S.: Windows for WorkGroup 3.11Fast Page DRAM: Micron 16M 70ns

(Sources from: SIS company's R&D lab)


Universal Serial Bus

Q: What is USB? What are its specifications?

A: USB is the abbreviation for Universal Serial Bus. This was developed by Compaq, Digital Equipment, IBM, Intel, Microsoft, NEC and Northern Telecom.

Transfer Rate12 Mb/s
Devices Supported63
Device TypesTelephony, Audio, KBD, etc.
Hub Support8-port hubs
Transfer TypesIsochronous, Asynch, Asynch-Block
CablingVCC, GND, SData+, SData-
Hot-Plug Device SupportYes

Q: What are the objectives of USB?


Q: How is USB implemented?

A: USB is based on a tree architecture, where each device attached may be a hub or a peripheral. Each device has a cable attached to it allowing any USB device to be plugged into an open USB port. Devices may either be externally powered, or may be powered by the bus. USB consists of:



last updated November 15, 1996

[Contents Page | Mail ]